Act 1
AI’s New Memory — Beyond HBM & SRAM, Without EUV
A new frontier of AI memory — approaching the bandwidth per watt of SRAM, going beyond HBM-class capacity — using 3D and materials innovations that leapfrog leading nodes while requiring no EUV lithography, built in fabs the world already has. Sampling this year. Fully allocated for 2027. Scaling in America from 2028.
Scarcity
Consider a thought experiment: everyone in the world owns enough memory and compute to power a personal agent or a humanoid in their home with the genius of Einstein and the empathy of Oprah. Today, each person would have to spend ~$300,000, or as much as a median American house, to purchase the compute, and burn ten households' worth of electricity to run our closest equivalent AI mind. Across eight billion people, that's eighty terawatts or 25x the planet's electricity generation — and a yearly manufacturing capacity that would cost the GDP of the entire planet to set up.
Even in today's centralized world where users share compute, with demand able to grow 10x in a year, the world is not able to make enough chips and does not have the energy to power the chips it makes. So intelligence is rationed, and we live in a world where more than 99% of people have still never used frontier intelligence¹.
This scarcity of chips– and these days, especially memory chips— along with the energy to turn them on, is the binding constraint preventing a future where exponentially rising intelligence from machines gives everyone the superpower to solve humanity's biggest problems.
A different way is possible.
What we've always done well, and especially in America, is invent. We founded Kepler on three convictions most considered impossible — and spent seven years proving them:
It is possible to re-invent chip manufacturing so that the capex for building advanced chips drops by an order of magnitude and useful inference compute per watt goes up by multiple orders of magnitude. We believe this is possible by taking advantage of the physics of the memories and devices.
It is possible to build these advanced AI chips without a dependence on EUV — and thus to use existing fabs and fab capacity to build chips that leapfrog advanced nodes. Such a new technology fundamentally changes the cost of computers by changing the cost of the factories which produce them.
Furthermore, it is possible to do so within the mainstream paradigm of digital computing - enabling the next generation of computer architectures with new physics while preserving all of the great software, logical architecture, and fab infrastructure we have built over the last six decades and algorithms invented1 on top of centuries of foundational mathematics2.
It is possible to be Lina Bo Bardi for computing: to take the fabs and architectures the world has already built, push them to the limits of physics, and turn them into a palace for the people.
Energy: Memory — and the associated data movement between memory and the processor — is the main performance and energy bottleneck for AI inference. Shuttling data from memory over a thin pipe of wires to the processor costs one to two orders of magnitude more energy than doing the basic arithmetic on that data itself. And beyond moving the data, the energy of storing it in memory and crunching it in the processor, is limited by the energy of fundamental transistor building blocks that make up the memory and processor. The energy of this transistor has mostly stopped improving. Unlike the miraculous times of Moore’s law past, we no longer get Dennard’s scaling: the gift gave us lower voltages “for free” as we shrunk the transistor. Transistor energy goes as V2 and so the inability to reduce this voltage without degrading performance significantly is a major obstacle to reducing the energy intrinsic to the memory and logic processor themselves.
Manufacturing capacity: Today's dominant approach — shrinking transistors to pack more devices, and thus more memory bits and arithmetic logic units, into each mm² — has run into the exploding capex of EUV: $200M-$400M a machine, $20B–$40B a fab, compounded by ever increasing process complexity of new transistors3. The industry makes a $200B-a-year bet: that it can spend three to five years building each new fab, and that by the time the doors open, AI demand will have grown enough to justify the investment. The fabs also take late stage technical risk in betting that the pathfinding technology actually scaled to volume and yield. Often bets are made well ahead of derisking the late stage manufacturing. Sized against that risk, it (quite rationally!) grows capex ~20% vs an AI demand that can grow 10x in a year and has no ceiling in practice as capabilities get stronger.
So in the current system, scarcity is built in. The perceived risk driven by the expensive, long duration investments makes supply structurally self-limiting. The scarcity is further extended by the installation time and lead times of the complex tools.
Start with Memory
Across both energy and manufacturing capacity, memory is the main bottleneck. For inference, improving other subsystems before memory gives gains diluted by Amdahl's Law . Hence Kepler’s made a bet to start with with memory long before SRAM scaling formally stopped and DRAM/HBM were understood in the mainstream as AI critical technology.
On energy, fixing data movement unlocks an order of magnitude in inference compute per watt for decode. On cost, memory and packaging dominate with at least 60–80% of the bill of materials of an AI machine.
To solve the energy and memory Bandwidth challenge, we use novel 3D manufacturing techniques that fit more chips, and fit them more closely, within a fixed footprint. More memory capacity per package, so fewer chips burning less power are needed to hold a model, and compute sits closer to memory, so every bit travels less and burns less energy. Placing them closer to the compute with 3D integration also allows many more interconnects than is traditionally possible with 2D or 2.5D system, allowing for much higher bandwidth, at reduced energy cost. In the long term, we update the transistor itself to bring back voltage scaling and enable more than an order of magnitude energy reduction. Our approach includes breakthroughs for the known thermal and power challenges that have held 3D back and will continue to limit any straightforward attempts. The Kepler team includes people who co-created one of the industry's first high-volume 3D chip-stacking technologies and have scaled seven generations of DRAM onto millions of wafers.
To solve the manufacturing capacity challenge - the key is that we avoid or reduce the dependency on EUV for increasing effective device density: novel low-voltage, CMOS-compatible materials let us use the z-dimension, so instead of shrinking transistors with EUV, we stack novel devices on top of transistors to get more devices per mm² that build up denser memory and logic functions. We also use 3D techniques between chips that relieve the need for EUV. Because these new process steps bolt onto fabs that already exist — a small Kepler fablet beside the main fab — an existing fab can leapfrog leading nodes by multiple generations with a set up period of months to a year vs multiple years and at a tenth of the capex compared to a new advanced node.
Just like Uber showed the world it had more taxis than it thought, Kepler believes the world has more usable advanced chip fab capacity than it knows.
With these approaches, Kepler will deliver a new frontier of AI memory — approaching the bandwidth per watt of SRAM while going up to 10x beyond the capacity of HBM — all without EUV lithography, and able to be built in America. Our memories are compatible with mainstream digital compute architectures, targeting usage as superior HBMs and SRAMs as well as intermediate tiers. This is working silicon in a major American fab's production flow — seven years in the making — and a major American foundry is both our manufacturing partner and our investor.
We're taking orders for our first AI memory product now — sampling by the end of this year — and are fully allocated for 2027. Next up is scaling: allocating capacity for 2028–30, with critical development and manufacturing done here in America. And we are building a deep ecosystem of partners across the value chain — from ASIC and GPU makers to system ODMs to clouds — working all the way from the chip to the rack to the datacenter, so that everyone deploying AI at scale can ultimately run with Kepler inside.
Beyond memory, we will apply the same materials and manufacturing approaches to logic — pushing the switching energies of atomic digital building blocks closer to the Landauer limit. Kepler's goal is to push chip energy efficiency and manufacturing capacity — the two constraints on AI becoming a broad utility — to the limits of physics, and to accelerate the delivery of frontier intelligence from under 1% of humanity to everyone.
In the limit — starting with memory, then proceeding to logic — Kepler moves us from a world of compute scarcity towards a world of compute abundance, with more of it manufactured in America and in countries that expand the liberalizing circle of democracy.
The world is way better off when we give power & intelligence to the people. When everybody can dream with the dream machine. When everyone can become an Einstein and a Mozart, taking on humanity's biggest challenges by pairing their human creativity with the exponentially rising intelligence from our magnificent computers.
Onwards. Towards Computing for everyone. At the limits of physics.
Notes
- 1
Knuth, D.E., 2005. The art of computer programming. Pearson Education.
↩ - 2
D. E. Knuth, “Algorithms in Modern Mathematics and Computer Science,” in Algorithms in Modern Mathematics and Computer Science, Lecture Notes in Computer Science, vol. 122, Springer, 1981, pp. 82–99
↩ - 3
Cao, W., Bu, H., Vinet, M., Cao, M., Takagi, S., Hwang, S., Ghani, T. and Banerjee, K., 2023. The future transistors. Nature, 620(7974), pp.501-515.
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